Tue, 19 Feb 2019 11:08:23 +0100

1 files changed, 28 insertions, 3 deletions

diff --git a/VHDL.wiki b/VHDL.wiki
index 737b2dc..13f48d7 100644
--- a/VHDL.wiki
+++ b/VHDL.wiki
@@ -117,15 +117,40 @@ Allting i VHDL är paralellt by default, dock finns:
 
 == Annat trevligt ==
 
+{{{VHDL
+entity mux is
+    port (d : in std_logic_vector (0 to 3);
+          s : in std_logic_vector (1 downto 0);
+          y : out std_logic_vector);
+end entity mux;
+}}}
+
 === with-select-when ===
 
+Är begränsad till att högerledet måste vara ett "simpelt" uttryck.
+
+{{{VHDL
+architecture behavior1 of mux is
+begin
+    with s select
+        y <= d(0) when "00",
+             d(1) when "01",
+             d(2) when "10",
+             d(3) when others;
+end architecture behavior1;
+}}}
+
 === when-else ===
 Tillåter "krångliga" uttryck i högerledet.
 
 Första sanna villkoret bestämmer. Allting körs parallellt?
 
 {{{VHDL
-y <= d(0) when s = "00" else
-     d(1) when s = "01" else
-     d(2);
+architecture behavior2 of mux is
+begin
+  y <= d(0) when s = "00" else
+       d(1) when s = "01" else
+       d(2) when s = "10" else
+       d(3);
+end architecture behavior2;
 }}}