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-rw-r--r-- | VHDL.wiki | 6 |
1 files changed, 4 insertions, 2 deletions
@@ -29,11 +29,13 @@ end architecture namn2; == Exempelkrets == -$$ \begin{aligned} +$ +\begin{aligned} \text{låt} x &= a \wedge b \\ y &= a \wee b : c = \neg (x \wee y) -\end{aligned} $$ +\end{aligned} +$ {{{vhdl entity knet is |